A wide variety of implantable medical devices (IMDs) that employ electronic circuitry for providing electrical stimulation of body tissue and/or monitoring a physiologic condition are known in the art. A number of IMDs of various types deliver electrical stimulating pulses to selected body tissue and typically comprise an implantable pulse generator (IPG) for generating the stimulating pulses under prescribed conditions and at least one lead bearing a stimulation electrode for delivering the stimulating pulses to the selected tissue. For example, cardiac pacemakers and implantable cardioverter/defibrillators (ICDs) have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of malignant tachyarrhythmias. Other IMDs have been developed for applying electrical stimulation or other therapies, e.g., drugs, to nerves, the brain, muscle groups and other organs and body tissues for treating a variety of conditions.
Current IMD operating system architectures typically are embodied in two or more ICs and discrete components mounted to one (or more) substrate employing hybrid fabrication circuitry techniques. Certain of the ICs or circuitry on a particular IC perform analog functions, input signal processing, and output therapy delivery. Digital logic ICs or circuitry may be formed employing complementary metal oxide semiconductor (CMOS) fabrication technology. The digital logic ICs perform signal processing, timing, and state change functions embodying Boolean logic timed synchronously by a system-wide clock.
Even with these improvements, such digital logic ICs including those assembled from various clocked components such as logic gates, flip-flops, latches, and other Boolean logic blocks used in IMD system architectures suffer from several limitations and disadvantages. It is necessary to route clock distribution over the complete IC chip area as a clock tree of discrete electrical conductors or lines to reach all clocked components. As the size and complexity of ICs increases, so do the pressures on designing clock trees for the circuits. Designers face an increasing number of components that need to deliver, act on and receive suitably timed signals.
There are various automated techniques for designing clock trees based on an IC which has been defined in terms of its logical design and which is to be implemented physically. Given the positions of the components within an IC layout, a clock tree synthesis (CTS) tool automatically designs a clock tree for distributing a clock signal to the components. The conventional CTS tools place clock tree delay elements at selected clock lines of the clock tree based on an estimate of the signal path delay in each clock line with the intent of balancing the clock tree. However, each clock tree delay element increases the current consumption of the IC and also adds to the size of the IC layout. There remains a need for design techniques that simplify the design of the clock tree in an IC and reduce the power consumption of the IC.